1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device. More particularly, this invention relates to a trench type flash memory device and the method of fabricating the same.
2. Description of Related Art
Memory device, by the name, is a type used to store information and data. As microprocessor becomes more and more powerful and the programming and calculation performed by software become more and more complicated, the demand for memory devices becomes even higher. In order to expand the capacity and lower the cost of memory devices to accommodate the higher demand for memory devices, The prevailing tendency to increase the device integration in the semiconductor industry has always been the driving force of a continued pursuit of technology and manufacturing process in the fabrication of memory devices.
As an example, flash memory device has been widely used in personal computers and other electronic equipment as the memory device for storing, reading and erasing information, and more advantageously, retaining the information even when the power is off.
A typical flash memory device is generally designed to have a stack-gate structure, which includes a tunneling oxide layer, a polysilicon floating gate for storing charges, an ONO (Oxide-Nitride-Oxide) dielectric layer and a polysilicon control gate to control the reading/writing of information. To perform the programming or the erasing operation on a flash memory device, the source, the drain and the control gate will be appropriately biased to either inject electrons into or to eject electrons from the polysilicon floating gate.
In general, the mode of electron injection for flash memory devices can be classified as Channel Hot-Electron Injection (CHEI) and F-N (Fowler-Nordheim) Tunneling, etc. The operating mode of programming and erasing varies depending on whether electrons are being injected and ejected.
Usually, during an operation of a flash memory device, the greater the gate-coupling ratio (GCR) between the floating gate and control gate, the lower the operation voltage is required. The operational speed and efficiency of the flash memory device are thus greatly increased. The methods of increasing the GCR include increasing the overlapped area between the floating gate and the control gate, reducing the dielectric thickness between the floating gate and the control gate, and increasing the dielectric constant (k) of the dielectric layer between the floating gate and the control gate, etc.
However, accompanying the continuous increase in integration in integrated circuits with a miniaturization of the device dimension, it is also necessary to reduce the cell size of a flash memory device in order to increase the level of integration. The reduction of memory cell size can be achieved by, for example, reducing the gate length of the memory cell and the distance between word lines. However, the reduction of the gate length of the memory cell will shorten the channel length under tunneling oxide, and thus will severe the short channel effect (SCE), leading to an abnormal punch through between source and drain. In addition, during the fabrication process of a flash memory cell, the problem of critical dimension also occurs in the course the photolithography process, which then will further limit the reduction of memory cell dimension.